DISPLAY PANEL

A display panel (110) according to embodiments of the disclosure may comprise a substrate (SUB) in which a display area (DA) and a non-display area (NDA) are divided, a gate driving circuit (130) disposed on the substrate (SUB) and disposed in a gate driving circuit area (GIPA) within the non-display area (NDA), a plurality of gate clock lines (GCLKL) disposed on the substrate (SUB) and disposed in a first line area (LA1) positioned outside the gate driving circuit area (GIPA) in the non-display area (NDA), an overcoat layer (OC) disposed on the plurality of gate clock lines (GCLKL) and the gate driving circuit (130), a cathode electrode (CE) disposed in the display area (DA) and extending to the non-display area (NDA), and a load deviation compensation pattern (COMP) overlapping the plurality of gate clock lines (GCLKL).