SPARSITY-AWARE COMPUTE-IN-MEMORY

Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold;...

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Bibliographische Detailangaben
Hauptverfasser: SRIVASTAVA, Ankit, MIRHAJ, Seyed Arash, WADHWA, Sameer, LI, Ren
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold; disabling one or more bit cells in the CIM array based on the sparsity of the input data prior to processing the input data; processing the input data with bit cells not disabled in the CIM array to generate an output value; applying a compensation to the output value based on the sparsity to generate a compensated output value; and outputting the compensated output value.