LOGIC GATE CIRCUIT, LATCH, AND TRIGGER

This application provides a logic gate circuit, a latch, and a flip-flop, relates to the field of logic circuits, and provides a logic gate circuit that is based on an NFET. The logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. The pull-up network includes a first NFET. The first NFET includes a first gate and a second gate. A first electrode of the first NFET and the first gate are connected to the first voltage end. A second electrode of the first NFET and the second gate are connected to the signal output end. The pull-down network includes a second NFET. The pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. The pull-down network is configured to: control the second NFET based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.