SEMICONDUCTOR DEVICES WITH VOLTAGE ADJUSTMENT

A semiconductor device includes: a voltage clamping circuit (210) including a plurality of first elements operating upon receiving a voltage having a first level and configured to output a clamped signal (CS) swinging in the first level by adjusting a voltage of an external input signal (EIS) swinging in a second level more than twice the first level; a first buffer circuit (220) configured to buffer the clamped signal (CS); a level down shifter circuit (230) configured to reduce the voltage of the clamped signal (CS) and output an internal input signal (IIS) swinging in the first level between a predetermined reference voltage (VSS) and a first power supply voltage (VDD) higher than the reference voltage (VSS); and a second buffer circuit (240) configured to buffer the internal input signal (IIS) and transmits the internal input signal (IIS) to a core circuit (250).