PACKAGE FOR A LATERAL POWER TRANSISTOR

A transistor package for a power transistor chip includes the power transistor chip having a first side and a second side opposite the first side. The first side comprises a source electrode metallization, a drain electrode metallization and a gate electrode metallization. The package further includes a multi-layer laminate substrate to which the power transistor chip is connected. The multi-layer laminate substrate comprises a first structured metal layer facing the first side of the power transistor chip and being electrically connected to the source electrode metallization, the drain electrode metallization and the gate electrode metallization, a second structured metal layer comprising a source package terminal pad, a source sense package terminal pad, a drain package terminal pad and a gate package terminal pad, at least one insulating layer disposed between the first structured metal layer and the second structured metal layer, and a plurality of vias running through the insulating layer and connecting segments of the first structured metal layer to the terminal pads of the second structured metal layer. The first structured metal layer, the second structured metal layer and the plurality of vias are designed such that a gate-source current path between the power transistor chip and the source sense package terminal pad is provided only on one of the first and second structured metal layers while a drain-source current path between the source electrode metallization of the power transistor chip and the source package terminal pad is at least on the other structured metal layer of the multi-layer laminate substrate.