LOW-STRESS DIELECTRIC LAYER, PLANARIZATION METHOD, AND LOW-TEMPERATURE PROCESSING FOR 3D-INTEGRATED ELECTRICAL DEVICE

An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.