LEVEL SHIFTER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

A level shifter comprises: a first stage (310, 410) including a plurality of first elements (N1-N4), the first stage (310, 410) being configured to receive a reference voltage (VSS) and comprising a first power supply with a first voltage (VDD) higher than the reference voltage (VSS); a second stage...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: JEON, Chanhee, KIM, Eonguk, JEONG, Jinsu
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A level shifter comprises: a first stage (310, 410) including a plurality of first elements (N1-N4), the first stage (310, 410) being configured to receive a reference voltage (VSS) and comprising a first power supply with a first voltage (VDD) higher than the reference voltage (VSS); a second stage (320, 420) including a plurality of second elements (P1-P4, N5-N8), the second stage (320, 420) being configured to receive the first voltage (VDD) and comprising a second power supply with a second voltage (2VDD) higher than the first voltage (VDD); and a third stage (330, 430) including a plurality of third elements (P5-P10), the third stage (330, 430) being configured to receive the second voltage (2VDD) and comprising a third power supply with a third voltage (3VDD) higher than the second voltage (2VDD); wherein a difference between the reference voltage (VSS) and the first voltage (VDD), a difference between the first voltage (VDD) and the second voltage (2VDD), and a difference between the second voltage (2VDD) and the third voltage (3VDD) are equal to each other, wherein the first stage (310, 410) is configured to receive an input signal (IN1, IN2) swinging between the reference voltage (VSS) and the first voltage (VDD), wherein the second stage (320, 420) is configured to output a first output signal (OUT1) swinging between the first voltage (VDD) and the second voltage (2VDD), and wherein the third stage (330, 430)is configured to output a second output signal (OUT2) swinging between the second voltage (2VDD) and the third voltage (3VDD).