SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR CONTROLLING MEMORY

Memory controllers and methods of controlling memory are described.One such apparatus comprises a system controller and a plurality of memory volumes configured to receive a shared chip enable signal from the system controller. Each memory volume comprises a number of memory units, which are configured to activate responsive to detecting a transition of a state of the shared chip enable signal from a high state to a low state. Responsive to a cycle type of a next cycle issued by the system controller subsequent to the transition of the state of the shared chip enable signal being a volume select command cycle, a target memory volume indicated by the volume select command is selected. Responsive to the cycle type of the next cycle issued by the system controller being a command cycle other than a volume select command cycle, a previously selected memory volume is re-selected.