SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORAGE BITS

SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORAGE BITS

A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second n...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: WILLIAMS, , Jacob T, ALAM, , Syed M
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Beschreibung
Zusammenfassung:A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.