NON-VOLATILE MEMORY DEVICE AND CORRESPONDING METHOD OF OPERATION

In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles (6) arranged horizontally. Each tile (6) includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder (90) is configured to receive a set of encoded address signals (ADD_LS[1:0], ADD_LY[2:0], ADD_LX[2:0], ADD_PX[3:0]) to produce pre-decoding signals (LS[3:0], LY[7:0], LX[7:0], PX[15:0]). A central row decoder (12) is arranged in line with the plurality of tiles (6), receives the pre-decoding signals and produces level-shifted pull-up (PullUp) and pull-down (WLD) driving signals for driving the word lines. First buffer circuits (30) are arranged on a first side of each tile (6). Each of the first buffer circuits (30) is coupled to a respective word line, receives a level-shifted pull-up driving signal (PullUp) and a level-shifted pull-down driving signal (WLD), and selectively pulls up or pulls down the respective word line as a function of the values of the received signals. Second buffer circuits (40) are arranged on a second side of each tile (6). Each of the second buffer circuits (40) is coupled to a respective word line, receives a level-shifted pull-down driving signal (WLD), and selectively pulls down the respective word line as a function of the value of the received signal. The pre-decoding signals are in the voltage range of 0 V to about 0.9 V, and the level-shifted pull-up and pull-down driving signals (PullUp, WLD) are in the voltage range of 0 V to a tile supply voltage (VXSECTOR) of the memory sector.