INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS

Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor comprises: fetch circuitry to fetch a single multiply-accumulate (MAC) instruction having fields to indicate an opcode, a destination, a first source vector having a first element width, and a second source vector having a second element width that is smaller than the first element width; decode circuitry to decode the fetched single MAC instruction; and a single instruction multiple data (SIMD) execution circuit to execute the single MAC instruction and perform multiply-accumulate operations within each processing lane of a plurality of processing lanes, the multiply-accumulate operations in each processing lane including: multiplying a subset of elements of the first source vector by corresponding elements of the second source vector to produce a corresponding subset of products, and accumulating the subset of products with an accumulation data element corresponding to the processing lane to generate a result data element corresponding to the processing lane, the result data element each having a width greater than the first element width and the second element width.