CONVOLUTION HARDWARE ACCELERATOR

A device includes integer multiplier circuits and a multiplexer circuit provides portions of mantissas of feature elements and portions of mantissas of weight elements to respective integer multiplier circuits, wherein the feature elements and the weight elements are floating-point data types, and wherein each integer multiplier circuit multiplies a respective portion of the mantissa of a feature element by a respective portion of the mantissa of a weight element to generate a partial product. A first shift circuit shifts bits of the partial products based on exponents of the feature elements and of the weight elements, and a first integer adder circuit adds the shifted partial products to generate a sum. A composition circuit generates an output element based on the sum generated by the first integer adder circuit, the exponents of the plurality of feature elements, and the exponents of the plurality of weight elements.