HARDWARE ACCELERATOR FOR FLOATING-POINT OPERATIONS

A device includes a memory storing a first lookup table of entries each comprising a starting index value and a number of samples corresponding to a respective segment of a function and a second lookup table of entries each comprising a respective sampled mantissa from the function. An interpolation logic circuit retrieves from the first lookup table a starting index value and a number of samples corresponding to a segment of the function corresponding to an input mantissa from an input floating-point element, retrieves from the second lookup table a first sampled mantissa and a second sampled mantissa based on the starting index value and the number of samples retrieved from the first lookup table and the input mantissa, and interpolates an output mantissa.