WAFER LEVEL CHIP SCALE PACKAGE WITH SIDEWALL PROTECTION

WAFER LEVEL CHIP SCALE PACKAGE WITH SIDEWALL PROTECTION

A wafer level chip scale package (10) includes a bare silicon die (100) having an active surface (S1), a rear surface (S2) opposite to the active surface (S1), and a sidewall surface (SW) between the active surface (S1) and the rear surface (S2). The bare silicon die (100) includes a backside corner...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHEN, Yu-Tung, TSAO, Pei-Haw, FAN, Kuo-Lung
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A wafer level chip scale package (10) includes a bare silicon die (100) having an active surface (S1), a rear surface (S2) opposite to the active surface (S1), and a sidewall surface (SW) between the active surface (S1) and the rear surface (S2). The bare silicon die (100) includes a backside corner (BC) between the rear surface (S2) and the sidewall surface (SW). A plurality of pads (101) is disposed on the active surface (S1). A plurality of conductive elements (110) is disposed on the plurality of pads (101), respectively. A backside tape (220) is adhered to the rear surface (S2) by using an adhesive layer (210). The adhesive layer (210) and the backside tape (220) protrude beyond the sidewall surface (SW) of the bare silicon die (100). The adhesive layer (210) extends along the sidewall surface (SW) and wraps around the backside corner (BC).