SWITCHABLE TERMINATION RESISTANCE CIRCUIT

The disclosure relates to a switchable termination resistance circuit for a transceiver physical layer interface. Example embodiments include a switchable termination resistance circuit (1101) for a transmission line transceiver (1301), the switchable termination resistance circuit (1101) comprising...

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Bibliographische Detailangaben
Hauptverfasser:	MOURET, Guillaume, HUOT-MARCHAND, Alexis N
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	The disclosure relates to a switchable termination resistance circuit for a transceiver physical layer interface. Example embodiments include a switchable termination resistance circuit (1101) for a transmission line transceiver (1301), the switchable termination resistance circuit (1101) comprising: first and second terminals (TXP, TXN) for connection to a transmission line (803); first and second NMOS termination resistance switches (Mnsw1, Mnsw2) having source connections connected together at a midpoint node (1103) and gate connections connected to an input node (1104); a first resistor (R1) connected between the first terminal (TXP) and a drain connection of the first NMOS termination resistance switch (Mnsw1); a second resistor (R2) connected between the second terminal (TXN) and a drain connection of the second NMOS termination resistance switch (Mnsw2); a Zener diode (Dz1) having a cathode side connected to the input node (1104) and an anode side connected to the midpoint node (1103); and a branch (1107) comprising a second Zener diode (Dz2), a branch diode (D3), a branch NMOS switch (Mn4) and a branch PMOS switch (Mp7) in a series connected arrangement between the midpoint node (1103) and a ground line (AGND).