METHOD FOR A SECURE EXECUTION OF INSTRUCTIONS

The present invention relates to a method for a secure execution of a first instruction by a processor of an electronic system comprising at least one memory configured to be coupled to the processor, and said processor comprises processor registers (103) and executions units comprising a load and s...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: TEGLIA, Yannick, COULON, Jean Roch, SINTZOFF, André
Format: Patent
Sprache:eng ; fre ; ger
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Beschreibung
Zusammenfassung:The present invention relates to a method for a secure execution of a first instruction by a processor of an electronic system comprising at least one memory configured to be coupled to the processor, and said processor comprises processor registers (103) and executions units comprising a load and store unit (104a),said method comprising:- fetching (S1) said first instruction in an execution pipeline of the processor,- determining (S2) if said first instruction to be executed is a load instruction to be protected for loading protected data and associated security information from said at least one memory to the processor registers or a store instruction to be protected for storing protected data and associated security information from the processor registers to said at least one memory,- when said first instruction to be executed is a load instruction to be protected or a store instruction to be protected, executing sequentially by said processor at least a first operation (S4), a second operation (S5) and a third operation (S6), wherein :* when said first instruction is a load instruction to be protected, said first operation is a load operation for loading said protected data from said at least one memory to said load and store unit, said second operation is a load operation for loading said security information associated to said protected data from said at least one memory to said load and store unit, and said third operation is a write operation for copying said protected data and said associated security information from said load and store unit to the processor registers,* when said first instruction is a store instruction to be protected, said first operation is a write operation for copying said protected data and said associated security information from the processor registers to said load and store unit, said second operation is a store operation for storing said copied protected data from said load and store unit to said at least one memory and said third operation is a store operation for storing said copied associated security information from said load and store unit to said at least one memory,said security information associated to protected data being data enabling to transform said protected data into plain data and/or integrity data enabling to verify integrity of said protected data.