SEMICONDUCTOR ELECTRONIC DEVICES INCLUDING SIDEWALL BARRIER LAYERS AND METHODS OF FABRICATING THE SAME

The present disclosure includes a semiconductor device comprising a substrate including a device surface and a patterned metallic electrode disposed on the substrate. The patterned metallic electrode is formed of one or more of copper, gold, and silver. The patterned metallic electrode comprises a l...

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Hauptverfasser: KIM, Hoon, MANLEY, Robert George
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MANLEY, Robert George
description The present disclosure includes a semiconductor device comprising a substrate including a device surface and a patterned metallic electrode disposed on the substrate. The patterned metallic electrode is formed of one or more of copper, gold, and silver. The patterned metallic electrode comprises a lower surface proximate to the substrate, an upper surface, and a sidewall extending between the lower surface and the upper surface a sidewall barrier layer extending over the sidewall. The sidewall barrier layer may be a manganese oxide barrier layer.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP4248491A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP4248491A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP4248491A13</originalsourceid><addsrcrecordid>eNqNy7EKwjAQgOEuDqK-w72AQ7WDjtfLxR6kiVxSxakUSSfRQn1_RPABnP7l-5fFGLkVCt50lIICO6akwQuB4YsQRxBPrjPiTxDF8BWdgxpVhRUc3lgjoDfQcmqCiRAsWKxVCNN3SQ1DxJbXxWIcHnPe_LoqwHKiZpunV5_nabjnZ373fK521aE6llju_yAfXyc0pQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR ELECTRONIC DEVICES INCLUDING SIDEWALL BARRIER LAYERS AND METHODS OF FABRICATING THE SAME</title><source>esp@cenet</source><creator>KIM, Hoon ; MANLEY, Robert George</creator><creatorcontrib>KIM, Hoon ; MANLEY, Robert George</creatorcontrib><description>The present disclosure includes a semiconductor device comprising a substrate including a device surface and a patterned metallic electrode disposed on the substrate. The patterned metallic electrode is formed of one or more of copper, gold, and silver. The patterned metallic electrode comprises a lower surface proximate to the substrate, an upper surface, and a sidewall extending between the lower surface and the upper surface a sidewall barrier layer extending over the sidewall. The sidewall barrier layer may be a manganese oxide barrier layer.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230927&amp;DB=EPODOC&amp;CC=EP&amp;NR=4248491A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230927&amp;DB=EPODOC&amp;CC=EP&amp;NR=4248491A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM, Hoon</creatorcontrib><creatorcontrib>MANLEY, Robert George</creatorcontrib><title>SEMICONDUCTOR ELECTRONIC DEVICES INCLUDING SIDEWALL BARRIER LAYERS AND METHODS OF FABRICATING THE SAME</title><description>The present disclosure includes a semiconductor device comprising a substrate including a device surface and a patterned metallic electrode disposed on the substrate. The patterned metallic electrode is formed of one or more of copper, gold, and silver. The patterned metallic electrode comprises a lower surface proximate to the substrate, an upper surface, and a sidewall extending between the lower surface and the upper surface a sidewall barrier layer extending over the sidewall. The sidewall barrier layer may be a manganese oxide barrier layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNy7EKwjAQgOEuDqK-w72AQ7WDjtfLxR6kiVxSxakUSSfRQn1_RPABnP7l-5fFGLkVCt50lIICO6akwQuB4YsQRxBPrjPiTxDF8BWdgxpVhRUc3lgjoDfQcmqCiRAsWKxVCNN3SQ1DxJbXxWIcHnPe_LoqwHKiZpunV5_nabjnZ373fK521aE6llju_yAfXyc0pQ</recordid><startdate>20230927</startdate><enddate>20230927</enddate><creator>KIM, Hoon</creator><creator>MANLEY, Robert George</creator><scope>EVB</scope></search><sort><creationdate>20230927</creationdate><title>SEMICONDUCTOR ELECTRONIC DEVICES INCLUDING SIDEWALL BARRIER LAYERS AND METHODS OF FABRICATING THE SAME</title><author>KIM, Hoon ; MANLEY, Robert George</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4248491A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM, Hoon</creatorcontrib><creatorcontrib>MANLEY, Robert George</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM, Hoon</au><au>MANLEY, Robert George</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR ELECTRONIC DEVICES INCLUDING SIDEWALL BARRIER LAYERS AND METHODS OF FABRICATING THE SAME</title><date>2023-09-27</date><risdate>2023</risdate><abstract>The present disclosure includes a semiconductor device comprising a substrate including a device surface and a patterned metallic electrode disposed on the substrate. The patterned metallic electrode is formed of one or more of copper, gold, and silver. The patterned metallic electrode comprises a lower surface proximate to the substrate, an upper surface, and a sidewall extending between the lower surface and the upper surface a sidewall barrier layer extending over the sidewall. The sidewall barrier layer may be a manganese oxide barrier layer.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR ELECTRONIC DEVICES INCLUDING SIDEWALL BARRIER LAYERS AND METHODS OF FABRICATING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-30T03%3A02%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KIM,%20Hoon&rft.date=2023-09-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP4248491A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true