FERROELECTRIC MEMORY AND STORAGE DEVICE

This application provides a ferroelectric memory and a storage device, to increase a density and improve a scale-down capability of a memory cell, and further reduce an area of the ferroelectric memory. The ferroelectric memory includes at least one bit cell. A bit cell in the at least one bit cell includes a plurality of ferroelectric capacitors and a first transistor. The first transistor includes a first gate, a first channel, and a first source and a first drain that are located at two ends of the first channel. One electrode of each of the plurality of ferroelectric capacitors is formed on the first gate.