RC OSCILLATION CIRCUIT

The present disclosure provides a resistor-capacitor (RC) oscillation circuit, including a first group of inverters, a second group of inverters, a latch, a delay circuit, and a third group of inverters. The first group of the inverters is connected to the delay circuit and is configured to generate a first signal A and a second signal B. An input end of the second group of the inverters is connected to an enable signal EN. An output end of the second group of the inverters is connected to the latch. An output end of the delay circuit is connected to the latch, and is configured to delay the first signal A and the second signal B. The latch is connected to the third group of the inverters and includes a first output end and a second output end, the latch receives the first delay signal DA and the second delay signal DB, the latch generates a first clock signal FB and a second clock signal FA and receives the first clock signal FB and the second clock signal FA. After a first clock signal FB is driven by the third group of the inverters, an output signal CLK is output by an output end of the third group of the inverters. The present disclosure avoids a situation that the circuit may not be recovered after entering a dead state, and is low in cost.