MEMORY AND DATA MIGRATION METHOD

A memory and a data migration method are disclosed, and relate to the storage field, to reduce time for implementing data migration between adjacent memory cell subarrays during in-memory computing in a DRAM, further reduce power consumption of the memory, and improve efficiency. The memory includes a sense amplifier and a switch unit are disposed in a row at spacings between adjacent memory cell subarrays. Between adjacent memory cell subarrays, a sense amplifier is disposed on one of every two adjacent bit lines, and the other bit line is connected to a switch unit in series. On a same bit line, the sense amplifier and the switch unit are alternately disposed between the memory cell subarrays.