NONVOLATILE MEMORY DEVICE INCLUDING COMBINED SENSING NODE AND CACHE READ METHOD THEREOF

A cache read method of a nonvolatile memory device (100) including a plurality of page buffer units (PBUO-PBUn-1) and cache latches, each page buffer units (PBUO-PBUn-1) having a sensing latch and a sensing node line is provided. The method comprises performing a first on-chip valley search, OVS, re...

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Bibliographische Detailangaben
Hauptverfasser: CHO, Hosang, CHO, Yongsung, KIM, Min Hwi
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:A cache read method of a nonvolatile memory device (100) including a plurality of page buffer units (PBUO-PBUn-1) and cache latches, each page buffer units (PBUO-PBUn-1) having a sensing latch and a sensing node line is provided. The method comprises performing a first on-chip valley search, OVS, read on a selected memory cell using a first sensing node line and a first sensing latch of a first page buffer unit of the plurality of page buffer units (PBUO-PBUn-1); storing first data sensed from the selected memory cell in the first sensing latch, the first data based on a result of the first OVS read; dumping the first data to sensing node lines of at least one page buffer unit, excluding the first page buffer unit, from among the plurality of page buffer units (PBUO-PBUn-1); and performing a second OVS read on the selected memory cell using the first sensing latch.