PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY

PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Van Doren, Stephen R, Pasdast, Gerald S, Munoz, Robert J, Liff, Shawna M, Elsherbini, Adel A, Gupta, Ritu
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises at least one of: a repeater circuitry and a fanout structure in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality.