DE-PRIORITIZING SPECULATIVE CODE LINES IN ON-CHIP CACHES

DE-PRIORITIZING SPECULATIVE CODE LINES IN ON-CHIP CACHES

Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic c...

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Bibliographische Detailangaben
Hauptverfasser: Soundararajan, Niranjan Kumar, Subramoney, Sreenivas, Moga, Adrian, Singhal, Ronak, Kallurkar, Prathmesh, Nori, Anant Vithal, Alam, Hanna, Rappoport, Lihu
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.