VOLTAGE REGULATOR CIRCUIT AND CORRESPONDING MEMORY DEVICE

A low-dropout voltage regulator circuit (40) is disclosed. The regulator receives an input voltage (Vcc) at an input node (400) and produces a regulated output voltage (VREG) at an output node (402). A first feedback network (R1, 412, 414) produces a feedback signal (VFB) indicative of the output voltage (VREG), and compares the feedback signal to a reference signal (VREF) to assert and de-assert a first pulsed control signal (COMP_OU-T) when the reference signal is higher and lower, respectively, than the feedback signal. A time-averaged value of the first pulsed control signal is a function of the difference between the reference signal and the feedback signal. A second feedback network (R2, 418, 420) produces a threshold signal (VTH) indicative of the input voltage, and compares the output voltage (VREG) to the threshold signal to assert and de-assert a second control signal (VCC_EN) when the threshold signal is higher and lower, respectively, than the output voltage. A charge pump circuit (408) is enabled (PMP_EN) if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage (VBL_SUPPLY) higher than the input voltage (Vcc). A first pass element (404a) arranged between the input node and the output node is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element (404b) arranged between the charge pump (408) and the output node (402) is selectively activated when the second control signal is de-asserted.