REUSING EXECUTED, FLUSHED INSTRUCTIONS AFTER AN INSTRUCTION PIPELINE FLUSH IN RESPONSE TO A HAZARD IN A PROCESSOR TO REDUCE INSTRUCTION RE-EXECUTION

Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-execution is disclosed. An instruction processing circuit detects fetched performance degrading instructions (PDIs) in an instruction pipeline that may cause a flushing of the instruction pipeline. In response to detecting a PDI, the instruction processing circuit is configured to store the PDI and/or its successor younger instructions in a pipeline execution refill circuit. In response to successful execution of such PDI and/or younger instructions, information about their input value(s) and produced output value(s) when executed are captured in the pipeline execution refill circuit. If a newly fetched instruction and its same input value(s) has been previously captured from the pipeline execution refill circuit, the instruction processing circuit is configured to inject the previously captured produced output value into the instruction pipeline without having to re-execute the newly fetched instruction.