INTEGRATED CIRCUIT WITH GALVANIC ISOLATION
An integrated circuit (1) with galvanic isolation (CT1, CT2) is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element (CT1) configured to separate a first isolation domain (100) from a second isolation domain (200) a...
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| creator | MORICI, Andrea FERIANZ, Thomas |
| description | An integrated circuit (1) with galvanic isolation (CT1, CT2) is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element (CT1) configured to separate a first isolation domain (100) from a second isolation domain (200) and a first channel (A) configured to transmit - in a first mode of operation (transparent mode) and across the first isolation element - a logic signal from a first input (INA) in the first isolation domain to a first output (OUTA) in the second isolation domain. The first channel is further configured to transmit - in a second mode of operation (configuration mode) and across the first isolation element - a serial data stream (MOSI) from the first input (INA) to a logic circuit (210) in the second isolation domain, wherein the logic circuit is configured to receive - in the second mode of operation - the serial data stream and to store configuration information included in the serial data stream in a memory. |
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In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element (CT1) configured to separate a first isolation domain (100) from a second isolation domain (200) and a first channel (A) configured to transmit - in a first mode of operation (transparent mode) and across the first isolation element - a logic signal from a first input (INA) in the first isolation domain to a first output (OUTA) in the second isolation domain. The first channel is further configured to transmit - in a second mode of operation (configuration mode) and across the first isolation element - a serial data stream (MOSI) from the first input (INA) to a logic circuit (210) in the second isolation domain, wherein the logic circuit is configured to receive - in the second mode of operation - the serial data stream and to store configuration information included in the serial data stream in a memory.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; PULSE TECHNIQUE ; TRANSMISSION ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230426&DB=EPODOC&CC=EP&NR=4170907A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230426&DB=EPODOC&CC=EP&NR=4170907A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MORICI, Andrea</creatorcontrib><creatorcontrib>FERIANZ, Thomas</creatorcontrib><title>INTEGRATED CIRCUIT WITH GALVANIC ISOLATION</title><description>An integrated circuit (1) with galvanic isolation (CT1, CT2) is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element (CT1) configured to separate a first isolation domain (100) from a second isolation domain (200) and a first channel (A) configured to transmit - in a first mode of operation (transparent mode) and across the first isolation element - a logic signal from a first input (INA) in the first isolation domain to a first output (OUTA) in the second isolation domain. The first channel is further configured to transmit - in a second mode of operation (configuration mode) and across the first isolation element - a serial data stream (MOSI) from the first input (INA) to a logic circuit (210) in the second isolation domain, wherein the logic circuit is configured to receive - in the second mode of operation - the serial data stream and to store configuration information included in the serial data stream in a memory.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><subject>TRANSMISSION</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDy9AtxdQ9yDHF1UXD2DHIO9QxRCPcM8VBwd_QJc_TzdFbwDPb3cQzx9PfjYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgEmhuYGlgbmjobGRCgBABbPJF4</recordid><startdate>20230426</startdate><enddate>20230426</enddate><creator>MORICI, Andrea</creator><creator>FERIANZ, Thomas</creator><scope>EVB</scope></search><sort><creationdate>20230426</creationdate><title>INTEGRATED CIRCUIT WITH GALVANIC ISOLATION</title><author>MORICI, Andrea ; FERIANZ, Thomas</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4170907A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2023</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><topic>TRANSMISSION</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>MORICI, Andrea</creatorcontrib><creatorcontrib>FERIANZ, Thomas</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MORICI, Andrea</au><au>FERIANZ, Thomas</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTEGRATED CIRCUIT WITH GALVANIC ISOLATION</title><date>2023-04-26</date><risdate>2023</risdate><abstract>An integrated circuit (1) with galvanic isolation (CT1, CT2) is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element (CT1) configured to separate a first isolation domain (100) from a second isolation domain (200) and a first channel (A) configured to transmit - in a first mode of operation (transparent mode) and across the first isolation element - a logic signal from a first input (INA) in the first isolation domain to a first output (OUTA) in the second isolation domain. The first channel is further configured to transmit - in a second mode of operation (configuration mode) and across the first isolation element - a serial data stream (MOSI) from the first input (INA) to a logic circuit (210) in the second isolation domain, wherein the logic circuit is configured to receive - in the second mode of operation - the serial data stream and to store configuration information included in the serial data stream in a memory.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY PULSE TECHNIQUE TRANSMISSION TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | INTEGRATED CIRCUIT WITH GALVANIC ISOLATION |
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