SYSTEMS AND METHODS FOR IMPLEMENTING CHAINED TILE OPERATIONS

Disclosed embodiments relate to systems and methods for implementing chained tile operations. In one example, an apparatus comprises a plurality of memory controllers, a level-two (L2) cache memory coupled to the plurality of memory controllers, a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, an interconnect coupled to the processor, and a bus controller coupled to the processor. The processor is to perform operations associated with an instruction indicating a first operation and a second operation, including to: perform the first operation on a first source matrix and a second source matrix to generate a third matrix, and perform the second operation on the third matrix and a fourth source matrix to generate a fifth matrix, wherein at least one of the first and second operations is a logical operation.