HANDLING MEMORY-LINES IN A MULTI-CORE PROCESSOR

Methods are provided of handling memory-lines affected by an instruction set to be executed in multi-core processor with affected memory-lines locked. These methods comprise: classifying affected memory-lines into classifications such that affected memory-line(s) mappable to same or affected memory-set are classified into same classification; requesting multi-line lock operation for each classification with several affected memory-lines, said multi-line lock operation including locking the several affected memory-lines in the private cache of the core executing the instruction set (or executor core) and loading the several affected memory-lines in the shared cache such that a sum of the several affected memory-lines and a number of pre-existing conflicting memory-lines loaded in the affected memory-set does not exceed memory-set capacity; and requesting, for each classification with single memory-line, locking the single memory-line in the private cache of the executor core. Systems, computing systems and computer programs suitable to perform said methods are also disclosed.