CLOCK SIGNAL DELAY PATH UNIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

A clock signal delay path unit includes a first delay cell (DC1) including a first root signal line (rsl1) for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line (rsll) without signal attenuation, and a second root signal line (rsl2) for delaying and transmitting the clock signal output from the first repeater, a second delay cell (DC2) including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell (DC3) including a first branch signal line (dsl1) for delaying and transmitting the inverted clock signal provided from the second delay cell (DC2), a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line (dsl2) for delaying and transmitting the inverted clock signal output from the second repeater.