MULTILEVEL WORDLINE ASSEMBLY FOR EMBEDDED DRAM

A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization...

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Bibliographische Detailangaben
Hauptverfasser:	TAN, Elliot, OGADHOH, Shem, SELL, Bernhard, WANG, Pei-Hua, SHARMA, Abhishek Anil, PIERCE, Kimberly, LAJOIE, Travis W, ALZATE VINASCO, Juan, KU, Chieh-Jen
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	ELECTRICITY
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.