SYSTEM AND METHOD OF CLOCK RECOVERY WITH LOW PHASE-ERROR FOR CARD EMULATION CLOCK-LESS NFC TRANSCEIVERS

Disclosed is a card clock recovery system (480; 500) for use in an NFC card transceiver (150; 450), wherein the NFC card transceiver (150; 450) is couplable to an NFC reader (110; 410). The card clock recovery system (480; 500) has: a phase lock loop (505) having: a phase/frequency detector (510), which is configured to receive a reference signal (512) provided at an RX port (476) of a matching network (475) during a receiving mode of the NFC transceiver (150; 450) or to receive a reference signal provided at the RX port (476) of the matching network (475) during a transmission mode of the NFC transceiver (150; 450), to receive a loop feedback signal (538), and to provide a phase error signal (518) that represents a phase difference between the reference signal (512) and the loop feedback signal (538); a loop filter (520) configured to receive a corrected phase error signal (756) that is derived from the phase error signal (518), and to provide a filtered corrected phase error signal (526); a controllable oscillator (530), which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal (534), which is provided as the card clock generation control signal (539) to a card clock generation unit (485) of an NFC card transceiver (150; 450), and as the loop feedback signal (538), via the loop feedback line (536), to the phase/frequency detector (510). The card clock recovery system (480; 500) further has a phase offset correction unit (700), which is configured to receive the phase error signal (518) provided by the phase/frequency detector and to provide the corrected phase error signal (756) to the loop filter (520), and which has a phase error sampling unit (720), a phase offset computation unit (730), and a phase subtractor unit (740).