METHODS AND DEVICES FOR MITIGATING PULLING IN A FRACTIONAL LOCAL OSCILLATOR SIGNAL GENERATION SCHEME

A radio-frequency integrated circuit (RFIC) configured to generate a synthesized clock includes a phase locked loop (PLL) configured to divide down a clock to a non-harmonic frequency; a plurality of multi-phase injection locked clock multipliers (ILCM) directly connected to a plurality of transceiver chains; wherein the PLL is further configured to distribute a divided down clock to at least one of the plurality of multi-phase ILCMs; wherein the plurality of multiphase ILCMs are configured to select a phase of and multiply the divided down clock to synthesize a desired harmonic frequency of the clock and suppress an undesired harmonic frequency of the clock.