PROCESSOR AND INSTRUCTION SET

The disclosure relates to a processor (100) and methods for operating a processor. The processor (100) comprises: a register file (101) comprising a plurality of register file addresses; a processing unit (102), configured to perform processing in accordance with a configuration defined by information stored in the register file (101); and an instruction sequencer (104). The instruction sequencer (104) is configured to control the processing unit (102) by retrieving a sequence of instructions from a memory, wherein each instruction comprises an opcode (201) and a subset of the instructions further comprise a data portion (202). For each instruction in the sequence of instructions, the instruction sequencer (104) performs an action defined by the opcode (201). The action for the subset of the opcodes (201) comprises writing the data portion (202) to a register file address defined by the opcode (201). The sequence of instructions comprises variable length instructions.