METHOD, SYSTEM, MEDIUM, AND PROGRAM PRODUCT FOR PATH VERIFICATION IN LOGIC CIRCUIT

A path verification method in a logic circuit includes determining a plurality of first paths that are to be tested in a design for test (DFT) mode (201), determining a plurality of second paths that are to be tested in a function mode (202), determining a third path in the plurality of first paths and the plurality of second paths that does not need to achieve optimal performance in the function mode (203), and setting a time sequence constraint for the third path in the function mode to cause the third path to achieve target performance within a number AA clock cycles. AA is less than or equal to a ratio of a clock frequency in the function mode to a clock frequency in the DFT mode. AA is a positive integer (204).