READ TIME REDUCTION WITH P-WELL BIAS IN MEMORY DEVICE

Apparatuses and techniques are described for reducing read time in a memory device. A source voltage signal, Vcelsrc, and a body voltage signal, Vp-well, of a source region and a p-well, respectively, of a substrate of a NAND string are controlled to reduce the channel resistance. Vcelsrc can be temporarily reduced, e.g., provided with a negative voltage kick, while Vp-well is non-decreasing during a read operation. The negative voltage kick decreases a body bias of the NAND string in its channel to reduce the channel resistance and increase the current. The negative voltage kick can be initiated when a bit line clamp transistor is made conductive to allow a current to flow in the NAND string. The magnitude and duration of the negative voltage kick can be adjusted based on various factors.