POWER-ON COMMUNICATION BETWEEN A HOST IC AND A CLIENT IC

A system (1) of a Host IC (2) connected via a wired data interface to a Client IC (3) to initiate the communication between the Host IC (2) and the Client IC (3) after power-on, wherein the Client IC (3) comprises a PLL stage (4) with a closed loop of a phase detector (5) a filter (6) and a voltage controlled oscillator (7) for the generation of the clock (C-clk) for the Client IC (3), which PLL stage (4) needs to be locked to the clock (H-clk) of the Host IC (2) for regular data communication via the wired data interface, which Client IC (3) comprises a power-on stage (4) to steer a switch (14) in the connection between the input of the clock (H-clk) of the Host IC (2) for the PLL stage (4) and the voltage controlled oscillator (7) of the PLL stage (4) to open the connection and to use the unregulated output clock of the free-running voltage controlled oscillator (7) in a time period after power-on for a power-on data communication via the wired data interface and to close the switch (14) after that time period for regular data communication.