NEURAL PROCESSING ELEMENT WITH SINGLE INSTRUCTION MULTIPLE DATA (SIMD) COMPUTE LANES

An architecture is disclosed for an neural processing element having single instruction, multiple data ("SIMD") compute lanes. The neural processing element includes compute lanes having multipliers configured to multiply a binary operand with another binary operand to generate a binary ou...

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Bibliographische Detailangaben

Hauptverfasser:	AMBARDEKAR, Amol A, CEDOLA, Kent D, MCBRIDE, Chad Balling, BOBROV, Boris, PETRE, George, WALL, Larry Marvin
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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