NEURAL PROCESSING ELEMENT WITH SINGLE INSTRUCTION MULTIPLE DATA (SIMD) COMPUTE LANES
An architecture is disclosed for an neural processing element having single instruction, multiple data ("SIMD") compute lanes. The neural processing element includes compute lanes having multipliers configured to multiply a binary operand with another binary operand to generate a binary ou...
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Sprache: | eng ; fre ; ger |
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Zusammenfassung: | An architecture is disclosed for an neural processing element having single instruction, multiple data ("SIMD") compute lanes. The neural processing element includes compute lanes having multipliers configured to multiply a binary operand with another binary operand to generate a binary output. The neural processing element also includes a single adder tree for summing the binary outputs of the hardware binary multipliers. The neural processing element also includes a storage element for storing a binary output of the single hardware binary adder tree. |
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