DUAL-BUFFER ARCHITECTURE-BASED TEXTURE MAPPING HARDWARE ACCELERATOR

The disclosure belongs to the technical field of Graphic Processing Unit (GPU) chip design, and particularly relates to a texture mapping hardware accelerator based on a double Buffer architecture. The texture mapping hardware accelerator includes an address calculation unit configured for calculating according to different texture address requests to obtain an address for accessing texel cache, a texel cache unit configured to obtain texels of corresponding cache lines from memory according to different request addresses, and a data calculation unit configured to carry out filtering processing according to different isotropic and anisotropic filtering modes and pixel processing for border_color and swizzle operation. With double Buffers, the calculation efficiency of texture index addresses may be improved, and when two layers of data need to be calculated at the same time, calculation may be started in parallel at the same time. When one enabled layer of data needs to be calculated, texels are indexed in parallel in an odd-even mode to guarantee data parallel calculation, so that the indexing time of the texel data is shortened, and the texel calculation efficiency is improved.