SYSTEM AND METHOD FOR MATRIX MULTIPLICATION INSTRUCTION WITH FLOATING POINT OPERAND WITH A SPECIFIED BIAS

A microprocessor system comprises a matrix computational unit and a control unit. The matrix computational unit includes a plurality of processing elements. The control unit is configured to provide a matrix processor instruction to the matrix computational unit. The matrix processor instruction spe...

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Bibliographische Detailangaben
Hauptverfasser: MCGEE, William, TALPES, Emil, DAS SARMA, Debjit
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:A microprocessor system comprises a matrix computational unit and a control unit. The matrix computational unit includes a plurality of processing elements. The control unit is configured to provide a matrix processor instruction to the matrix computational unit. The matrix processor instruction specifies a floating-point operand formatted using a first floating-point representation format. The matrix computational unit accumulates an intermediate result value calculated using the floating-point operand. The intermediate result value is in a second floating-point representation format.