MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

Methods and apparatus relating to memory controller techniques. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, and a processor communicatively coupled to the cache memory and the high-bandwidth memory, the processor to manage data transfer between the cache memory and...

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Bibliographische Detailangaben
Hauptverfasser: RANGANATHAN, Vasanth, GEORGE, Varghese, INSKO, Brent, PANNEER, Selvakumar, TANGRI, Saurabh, SINHA, Kamal, ANANTARAMAN, Aravindh, SURTI, Prasoonkumar, OULD-AHMED-VALL, ElMoustapha, RAY, Joydeep, COORAY, Niran, KOKER, Altug, HUNTER, Arthur, APPU, Abhishek R, STRIRAMASSARMA, Lakshminarayanan, ASHBAUGH, Ben, JANUS, Scott
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Methods and apparatus relating to memory controller techniques. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, and a processor communicatively coupled to the cache memory and the high-bandwidth memory, the processor to manage data transfer between the cache memory and the high-bandwidth memory for memory access operations directed to the high-bandwidth memory. Other embodiments are also disclosed and claimed.