METHOD AND SYSTEM FOR DETECTING OPEN/SHORT CIRCUIT ON PCB DESIGN LAYOUT, AND ELECTRONIC DEVICE

A method for detecting an open/short circuit on a PCB design layout, for use in detecting the accuracy of PCB design data. The method comprises: reading PCB data of a PCB design layout to be detected, and outputting an image of each PCB layer comprised in the PCB design layout (S1); performing first connectivity analysis on the image of each PCB layer to categorize solder pad patterns contacting in a same layer as a same sub-network group (S2); performing second connectivity analysis on each electroplating hole on a drill hole layer of the PCB design layout to categorize the sub-network groups where the solder pad patterns connected by each electroplating hole passing through different PCB layers are located as a same parent network group (S3); reading IPC netlist data of the PCB design layout to obtain a netlist network group where the solder pad patterns are located (S4); determining whether the netlist network relationship of the solder pad patterns is consistent with the network relationship on which the second connectivity analysis is performed (S5); if yes, determining that the PCB design layout does not have an open/short circuit problem (S6); and if not, determining that the PCB design layout has an open/short circuit problem (S7).