METHOD FOR WRITING IN A NON-VOLATILE MEMORY ACCORDING TO THE AGEING OF THE MEMORY CELLS AND CORRESPONDING INTEGRATED CIRCUIT

A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.