METHOD OF ONO INTEGRATION INTO A LOGIC CMOS PROCESS

Disclosed is a method comprising: forming above a surface on a substrate a stack of gate layers including at least two dielectric layers separated by at least one gate layer; forming a nonvolatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; forming on sidewalls of the first opening a charge-trapping layer; and forming on inside sidewalls of the charge-trapping layer a thin layer of semiconducting material, and substantially filling the first opening with a dielectric material separated from the stack of gate layers by the thin layer of semiconducting material the charge-trapping layer; and forming a MOS devices in a second region of the stack of gate layers.