INTER-CHIP LATENCY CHARACTERISTIC IN MULTI-CHIP SYSTEM

An inter-chip timing synchronization method comprising:for each pair of chips in a plurality of chips of a semiconductor device:determining a first one-way latency for transmissions from a first chip in the pair to a second chip in the pair of chips, anddetermining a second one-way latency for transmissions from the second chip in the pair to the first chip in the pair of chips;receiving, at a semiconductor device driver, the first one-way latency and the second one-way latency for each pair of chips;determining, by the semiconductor device driver and from the respective first one-way latency and the second one-way latency for each pair of chips, a loop latency between each pair of chips;adjusting, by the semiconductor device driver and for at least one pair of chips, a local counter of the second chip in the at least one pair of chips based on a characteristic inter-chip latency of the semiconductor device and the first one-way latency of the at least one pair of chips.