SERDES WITH JITTER INJECTION SELF STRESS MECHANISM

Devices and methods are provided for performing a high-frequency jitter self stress check on a receiver to assist with optimization. High-frequency jitter is injected into a clock signal recovered from a received data signal and used to sample the data signal. The injected jitter increases the bit e...

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Bibliographische Detailangaben
Hauptverfasser:	NIR, Ehud, KROTNEV, Petar Ivanov, WONG, Henry
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	Devices and methods are provided for performing a high-frequency jitter self stress check on a receiver to assist with optimization. High-frequency jitter is injected into a clock signal recovered from a received data signal and used to sample the data signal. The injected jitter increases the bit error rate (BER), making BER a more useful and quicker optimization metric in applications using low-noise communication links. Error correction is used to maintain acceptable output BER while the self stress check is in progress.