INERT ENVIRONMENT FUSIBLE LINKS

A micro-fuse assembly includes a substrate (42), a number of thin-film micro-fuses on the substrate (42), and a topping wafer (70) configured to sealingly engage to at least one of the substrate or the thin-film micro-fuses to define a cavity therebetween. The cavity is configured to encapsulate the...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	POTASEK, David P, BACKMAN, Roger Alan
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES MICROSTRUCTURAL TECHNOLOGY PERFORMING OPERATIONS PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS SEMICONDUCTOR DEVICES TRANSPORTING
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Beschreibung
Zusammenfassung:	A micro-fuse assembly includes a substrate (42), a number of thin-film micro-fuses on the substrate (42), and a topping wafer (70) configured to sealingly engage to at least one of the substrate or the thin-film micro-fuses to define a cavity therebetween. The cavity is configured to encapsulate the thin-film micro-fuses within an inert environment sealed within the cavity. A method of encapsulating a micro-fuse assembly within an inert environment using a topping wafer is also disclosed.