A SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASSOCIATED WITH MEMORY DEVICES

A selection device comprising: a multiplexer component; an input channel configured to couple at least the multiplexer component to a memory sub-system controller; a plurality of output channels coupled to the multiplexer component, wherein each of the plurality of output channels is further coupled to a respective memory device of a plurality of memory devices, and wherein each of the plurality of output channels is configured to transmit data between the multiplexer component and the respective memory device; and a decoder component coupled to the input channel and each of the plurality of memory devices, wherein the decoder component is configured to perform operations comprising: receiving, from the memory sub-system controller via the input channel, a signal comprising a first signal portion configured to enable the decoder component and a second signal portion configured to identify a particular output channel of the plurality of output channels that is to transmit the data between the multiplexer component and a corresponding memory device; decoding the received signal; and transmitting the decoded signal to each of the plurality of memory devices, wherein the decoded signal is to enable transmission of the data between the multiplexer component and the corresponding memory device via the particular output channel.