HARDWARE UNIT FOR PERFORMING MATRIX MULTIPLICATION WITH CLOCK GATING

Hardware units and methods to perform a matrix multiplication. The hardware units include: a multiplier stage comprising a plurality of multipliers, each multiplier configured to multiply a first data element and a second data element to produce a multiplication data element; one or more adder stages following the multiplier stage that form an adder tree to produce a sum of the multiplication data elements, each adder stage comprising one or more adders configured to add at least two data elements output by a previous stage to produce an addition data element; wherein at least one multiplier and/or at least one adder is preceded by a storage element corresponding to each bit of the data elements input to the at least one adder or the at least one multiplier; and control logic configured to: (i) clock gate all or a portion of the storage elements corresponding to a data element in response to determining that all or a portion of that data element can be treated as having a zero value; and (ii) for each storage element that is clock gated, cause a zero bit to be provided to the corresponding multiplier or adder..