INTERFACE FOR MEMORY HAVING A CACHE AND MULTIPLE INDEPENDENT ARRAYS

INTERFACE FOR MEMORY HAVING A CACHE AND MULTIPLE INDEPENDENT ARRAYS

The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controlle...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CONFALONIERI, Emanuele, MINOPOLI, Dionisio, FERRANTE, Gianfranco, BALLUCHI, Daniele, CAPRI, Antonino
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.